Testing embedded memories in telecommunication systems

Testing Embedded Memories in Telecommunication Systems

Testing Embedded Memories: A Survey

According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing system on chips (SoCs) content in the future, approaching 90% in in some cases. Therefore, the memory yield and quality will have a dramatic impact on the overall SoC cost and outgoing product quality. Meeting a high memory yield and quality requires understanding mem...

Testing and Diagnosing Embedded Content Addressable Memories

Embedded content addressable memories (CAMs) are important components in many system chips. In this paper two efficient March-like test algorithms are proposed. In addition to typical RAM faults, they also cover CAMspecific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N + W ) Compare operations to cover comparison and RAM faults (but does not fully cover the in...

Methodologies for testing embedded content addressable memories

This paper presents a design strategy for efficient and comprehensive testing of embedded dynamic content addressable memory (DCAM) where the address, data, and hit lines are not externally controllable or observable. Based on the design for testability approach, three algorithms are developed for testing common functional faults in CAM’s. The first algorithm provides a new method of detecting ...

Diagnostic Testing of Embedded Memories Based on Output Tracing

A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a given fault model. The approach is based on decomposition of functional memory faults into basic fault effects and output tracing. Output tracing involves storing all read operation results for defective memory cells and r...